1. Field of the Invention
The invention relates to a method of fabricating a landing pad, and more particularly, to a method of fabricating a landing pad for use in a bit line and a node contact with an improved patterning quality.
2. Description of the Related Art
In the fabrication process of a dynamic random access memory (DRAM) of an is integrated circuit, a bit line and a capacitor is respectively coupled with the source region and the drain region via a landing pad. The conventional method of fabricating a landing pad includes forming a polysilicon layer after the formation of a gate electrode on a substrate. The polysilicon layer is then patterned using photolithography and etching process to form the landing pads for the source and the drain regions. However, due to the uneven surface profile caused by the distribution of metal oxide semiconductor (MOS) transistors, the precision of the photolithography and etching process is degraded. Thus, to enhance the isolation between neighboring landing pads, spacers are formed on sidewalls thereof to increase the complexity of fabrication process.